An Efficient Design of Memory-Based Realization of FIR Digital Filter

In the last two decades, many efficient algorithmsand architectures have been introduced for the design of lowcomplexity bit-parallel multiple constant multiplications (MCM)operation which dominates the complexity of many digital signalprocessing systems. On the other hand, little attention has beengiven to the digitserial MCM design that offers alternative lowcomplexityMCM operations albeit at the cost of an increaseddelay. In this paper mainly addressing the problem of optimizing the gate-level area in digit-serial MCM designs and introduce highlevelsynthesis algorithms, design architectures, and a computeraideddesign tool. Experimental results show the efficiency of theproposed optimization algorithms and of the digit-serial MCMarchitectures in the design of digit-serial MCM operations andfinite impulse response filters.